1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, which can simplify fabricating processes for the semiconductor device.
2. Description of the Prior Art
Generally, a fabricating process for DRAMs of semiconductor devices is performed in an order of an isolation process, a gate electrode forming process, a bit line forming process, a capacitor forming process, and a metal wiring forming process.
FIGS. 1 and 2 show layout views for explaining a conventional method for manufacturing a semiconductor device. Herein, FIG. 1 shows a layout view of a semiconductor device for which a gate forming process and a landing plug forming process have been carried out. FIG. 2 shows a layout view of a semiconductor device for which a bit line contact forming process, a bit line forming process, a storage node contact forming process, and a storage node electrode forming process have been carried out after the gate forming and landing plug forming processes described with reference to FIG. 1.
Also, FIGS. 3a to 3i are sectional views taken along an A-B line shown in FIGS. 1 and 2. FIGS. 4a to 4e are sectional views taken along a C-D line shown in FIGS. 1 and 2. In addition, FIGS. 5a to 5d are sectional views taken along an E-F line shown in FIGS. 1 and 2.
As shown in FIGS. 1, 3a, and 4a, according to the conventional method for manufacturing a semiconductor device, a semiconductor substrate 1 having a field region (not shown) and an active region (not shown) is prepared. Subsequently, a shallow trench isolation (STI) process is performed with respect to the field region of the substrate 1, thereby forming an isolation layer. 2.
Then, as shown in FIGS. 1, 3b, and 4b, after forming a gate line 3 on the substrate including the isolation layer 2, a first insulating layer 4 for covering a structure of the gate line 3 is formed. After that, an ion implantation process is carried out with respect to an entire substrate by using the gate line 3 as a mask, thereby forming source/drain regions (S1/D1) between gate lines 3 formed on a lower substrate (shown in FIG. 1).
After that, as shown in FIGS. 3c and 4c, after performing a CMP process for the first insulating layer 4, the first insulating layer 4 is selectively etched, thereby forming a contact hole 5 for exposing the source region or the drain region. Subsequently, a conductive plug 6 filling the contact hole 5 is formed.
Then, as shown in FIG. 3d, after forming a second insulating layer 7 on an entire surface of the substrate including the conductive plug 6, the second insulating layer 7 is selectively etched as shown in FIG. 4d, thereby forming a bit line contact 8 for exposing the conductive plug 6.
After that, as shown in FIGS. 3e and 4e, after forming a bit line 9 for filling the bit line contact 8, a third insulating layer 10 is formed on an entire surface of a structure of the bit line 9. At this time, although it is not shown, an insulating spacer is formed at a side of the bit line 9, thereby preventing the bit line 9 from being subject to a circuit-short in relation to a capacitor during next processes.
Subsequently, as shown in FIGS. 3f and 5a, after forming a storage node contact 11 by selectively etching the third insulating layer and the second insulating layer, a landing plug 12 filling the storage node contact 11 is formed as shown in FIGS. 3g and 5b. 
Then, as shown in FIGS. 3h and 5c, a fourth insulating layer 13 is formed on an entire surface of the substrate including the landing plug 12.
After that, as shown in FIGS. 3i and 5d, after forming a contact hole 14 for exposing the landing plug 12 by selectively etching the fourth insulating layer, a storage node electrode 15 of a capacitor is formed in such a manner that the storage node electrode 15 is connected to the landing plug 12 while covering an inner wall of the contact hole 14. After that, a dielectric layer 16 and a plate electrode 17 are sequentially formed such that the storage node electrode 15 of the capacitor is covered with the dielectric layer 16 and a plate electrode 17.
Generally, since a bit line is aligned perpendicularly to a gate line, and a bit line contact must connect the bit line to a source region, it is preferred that the bit line contact is formed at the center of the source region.
However, according to a conventional process for manufacturing a semiconductor device, although a gate line forming process, a bit line forming process, and a capacitor forming process are sequentially performed after an isolation process, it is difficult to ideally align the bit line contact with respect to the source region, because the bit line passes over a drain region for forming the capacitor.
Also, since a bit line contact of a cell area cannot be simultaneously etched together with a bit line contact of a peripheral circuit area, a bit line contact process is performed twice. Accordingly, the process for manufacturing the semiconductor device is complicated. In addition, a landing plug is also formed in a drain of an active region so as to fabricate a capacitor connected to the drain by means of the landing plug, so that an additional landing plug forming process must be performed. Therefore, the process for manufacturing the semiconductor device is further complicated.